Picaxe PLL loaders

Two Picaxe based loaders were evaluated:

• VK3XDK / VK3HZ Agile-PLL
• VK4ADC X-locker

The only chips on hand were the current generation 08M2 and 14M2 chips, so an attempt was made to run the distributed code on the available chips using the Picaxe Editor v5.4.3. No attempt was made to alter the code to solve problems, other than disabling statements specifying earlier chip types.

VK3XDK / VK3HZ Agile-PLL

The distributed production code loaded and ran. (Note that there are many enhanced versions of this code circulating.)

Fig 1:

 Signals were observed on the /SENB lead and SCK lead, the SDATA output pin initialised but carried all zeros. Fig 1 shows the captured output data. Two 24 bit registers were loaded in about 680ms.

Fig 2:

Fig 2 shows a finer detail view of the SCK signal. The duration of the high is about 1ms, and the bit rate is about 70b/s.

VK4ADC X-locker

The code did not run on an 08M2. No attempt was made to resolve the issue.

Links

• PllLdr

Changes

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